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{'doi': '10.1049/ip-cds:20000197', 'member_id': '265', 'member': 'Institution of Engineering and Technology (IET)', 'container-title': 'IEE Proceedings - Circuits, Devices and Systems', 'primary-resource': 'https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20000197', 'tld': 'theiet.org', 'clearbit-logo': '/static/no_logo.svg', 'coaccess': [], 'multiple-resolution': [], 'type': 'JOURNAL ARTICLE', 'published_date': '2000', 'publication': 'IEE Proceedings - Circuits, Devices and Systems', 'title': 'Logical modelling of delay degradation effect in static CMOS gates', 'name': None, 'id': None, 'location': None, 'display_doi': 'https://doi.org/10.1049/ip-cds:20000197', 'grant_info': None, 'grant_info_funders': None, 'grant_info_funder_ids': '', 'grant_info_type': None, 'multiple_lead_investigators': [], 'multiple_co_lead_investigators': [], 'multiple_investigators': [], 'finances': [], 'project_description': None, 'award_amount': None, 'award_start': None, 'funding_scheme': None, 'internal_award_number': None, 'editors': None, 'authors': 'M.J. Bellido-Díaz | J. Juan-Chico | A.J. Acosta | M. Valencia | J.L. Huertas', 'chairs': None, 'supplementary_ids': None}
https://doi.org/10.1049/ip-cds:20000197
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